// *******************************************************************************************************
//! LIST | CONTEXT | NOTE
//! ---  | ---     | --- 
//! Company | Fpga Publish
//! Engineer| worker fu   
//! 
//! Create Date | 2024/11/22 20:09:18
//! Design Name | PL
//! Module Name | sfp_blck
//! Project Name| VIEW_EYES 
//! Target Devices| ZYNQ7010 & XCZU2CG & Kintex7 & A10
//! Tool Versions | vivado2021.1 & quartus2018
//! Description   | what it design?
//!         1     | 
//! Dependencies  | how it work?
//!         1     | 
//! Revision      | when it update?
//!          0.01 | File Created
//! Additional Comments | where it supoort?
//!          Xilinx     | https://www.xilinx-china.cn/
// *******************************************************************************************************
// ###################################################################################
// file include and scale define
`timescale 1ns / 1ps
module sfp_blck #(
    // -----------------------
    parameter MD_SIM_ABLE = 0, //! mode  of sim enable
    parameter WD_ERR_CODE = 4  //! width of err info 
   )(
    //! system signals
    input           i_sys_clk  , //! clock 
    input           i_sys_resetn,//! reset 
    
    //! error info feedback
    output   [WD_ERR_CODE-1:0]  m_err_sfp_code
);

// =========================================================================
// function and localparam to converation and calculate

// =========================================================================
// register and wire to time sequence and combine

// =========================================================================
// module / task / always / assign to drive logic and connect

atx_pll u0_atx_pll (
    .pll_powerdown     ( pll_powerdown     ),          //   input,  width = 1,     pll_powerdown.pll_powerdown
    .pll_refclk0       ( pll_refclk0       ),          //   input,  width = 1,       pll_refclk0.clk
    .tx_serial_clk     ( tx_serial_clk     ),          //  output,  width = 1,     tx_serial_clk.clk
    .pll_locked        ( pll_locked        ),          //  output,  width = 1,        pll_locked.pll_locked
    .pll_cal_busy      ( pll_cal_busy      ),          //  output,  width = 1,      pll_cal_busy.pll_cal_busy
    .mcgb_rst          ( mcgb_rst          ),          //   input,  width = 1,          mcgb_rst.mcgb_rst
    .tx_bonding_clocks ( tx_bonding_clocks )           //  output,  width = 6, tx_bonding_clocks.clk
);
phy_reset u0_phy_reset (
    .clock              ( clock               ),   //   input,  width = 1,              clock.clk
    .reset              ( reset               ),   //   input,  width = 1,              reset.reset
    .pll_powerdown      ( pll_powerdown       ),   //  output,  width = 1,      pll_powerdown.pll_powerdown
    .tx_analogreset     ( tx_analogreset      ),   //  output,  width = 1,     tx_analogreset.tx_analogreset
    .tx_digitalreset    ( tx_digitalreset     ),   //  output,  width = 1,    tx_digitalreset.tx_digitalreset
    .tx_ready           ( tx_ready            ),   //  output,  width = 1,           tx_ready.tx_ready
    .pll_locked         ( pll_locked          ),   //   input,  width = 1,         pll_locked.pll_locked
    .pll_select         ( pll_select          ),   //   input,  width = 1,         pll_select.pll_select
    .tx_cal_busy        ( tx_cal_busy         ),   //   input,  width = 1,        tx_cal_busy.tx_cal_busy
    .rx_analogreset     ( rx_analogreset      ),   //  output,  width = 1,     rx_analogreset.rx_analogreset
    .rx_digitalreset    ( rx_digitalreset     ),   //  output,  width = 1,    rx_digitalreset.rx_digitalreset
    .rx_ready           ( rx_ready            ),   //  output,  width = 1,           rx_ready.rx_ready
    .rx_is_lockedtodata ( rx_is_lockedtodata  ),   //   input,  width = 1, rx_is_lockedtodata.rx_is_lockedtodata
    .rx_cal_busy        ( rx_cal_busy         )    //   input,  width = 1,        rx_cal_busy.rx_cal_busy
);
native_phy u0_native_phy (
    .tx_analogreset          (tx_analogreset          ),               //   input,    width = 4,          tx_analogreset.tx_analogreset
    .tx_digitalreset         (tx_digitalreset         ),               //   input,    width = 4,         tx_digitalreset.tx_digitalreset
    .rx_analogreset          (rx_analogreset          ),               //   input,    width = 4,          rx_analogreset.rx_analogreset
    .rx_digitalreset         (rx_digitalreset         ),               //   input,    width = 4,         rx_digitalreset.rx_digitalreset
    .tx_cal_busy             (tx_cal_busy             ),               //  output,    width = 4,             tx_cal_busy.tx_cal_busy
    .rx_cal_busy             (rx_cal_busy             ),               //  output,    width = 4,             rx_cal_busy.rx_cal_busy
    .tx_serial_clk0          (tx_serial_clk0          ),               //   input,    width = 4,          tx_serial_clk0.clk
    .rx_cdr_refclk0          (rx_cdr_refclk0          ),               //   input,    width = 1,          rx_cdr_refclk0.clk
    .tx_serial_data          (tx_serial_data          ),               //  output,    width = 4,          tx_serial_data.tx_serial_data
    .rx_serial_data          (rx_serial_data          ),               //   input,    width = 4,          rx_serial_data.rx_serial_data
    .rx_is_lockedtoref       (rx_is_lockedtoref       ),               //  output,    width = 4,       rx_is_lockedtoref.rx_is_lockedtoref
    .rx_is_lockedtodata      (rx_is_lockedtodata      ),               //  output,    width = 4,      rx_is_lockedtodata.rx_is_lockedtodata
    .tx_coreclkin            (tx_coreclkin            ),               //   input,    width = 4,            tx_coreclkin.clk
    .rx_coreclkin            (rx_coreclkin            ),               //   input,    width = 4,            rx_coreclkin.clk
    .tx_clkout               (tx_clkout               ),               //  output,    width = 4,               tx_clkout.clk
    .rx_clkout               (rx_clkout               ),               //  output,    width = 4,               rx_clkout.clk
    .tx_pma_div_clkout       (tx_pma_div_clkout       ),               //  output,    width = 4,       tx_pma_div_clkout.clk
    .tx_parallel_data        (tx_parallel_data        ),               //   input,  width = 256,        tx_parallel_data.tx_parallel_data
    .tx_control              (tx_control              ),               //   input,   width = 32,              tx_control.tx_control
    .tx_err_ins              (tx_err_ins              ),               //   input,    width = 4,              tx_err_ins.tx_err_ins
    
    .unused_tx_parallel_data (unused_tx_parallel_data ),               //   input,  width = 256, unused_tx_parallel_data.unused_tx_parallel_data
    .unused_tx_control       (unused_tx_control       ),               //   input,   width = 36,       unused_tx_control.unused_tx_control
    .rx_parallel_data        (rx_parallel_data        ),               //  output,  width = 256,        rx_parallel_data.rx_parallel_data
    .rx_control              (rx_control              ),               //  output,   width = 32,              rx_control.rx_control
    .unused_rx_parallel_data (unused_rx_parallel_data ),               //  output,  width = 256, unused_rx_parallel_data.unused_rx_parallel_data
    .unused_rx_control       (unused_rx_control       ),               //  output,   width = 48,       unused_rx_control.unused_rx_control
    
    .tx_enh_data_valid       (tx_enh_data_valid       ),               //   input,    width = 4,       tx_enh_data_valid.tx_enh_data_valid
    .tx_enh_fifo_full        (tx_enh_fifo_full        ),               //  output,    width = 4,        tx_enh_fifo_full.tx_enh_fifo_full
    .tx_enh_fifo_pfull       (tx_enh_fifo_pfull       ),               //  output,    width = 4,       tx_enh_fifo_pfull.tx_enh_fifo_pfull
    .tx_enh_fifo_empty       (tx_enh_fifo_empty       ),               //  output,    width = 4,       tx_enh_fifo_empty.tx_enh_fifo_empty
    .tx_enh_fifo_pempty      (tx_enh_fifo_pempty      ),               //  output,    width = 4,      tx_enh_fifo_pempty.tx_enh_fifo_pempty
    .rx_enh_data_valid       (rx_enh_data_valid       ),               //  output,    width = 4,       rx_enh_data_valid.rx_enh_data_valid
    .rx_enh_fifo_full        (rx_enh_fifo_full        ),               //  output,    width = 4,        rx_enh_fifo_full.rx_enh_fifo_full
    .rx_enh_fifo_empty       (rx_enh_fifo_empty       ),               //  output,    width = 4,       rx_enh_fifo_empty.rx_enh_fifo_empty
    .rx_enh_fifo_del         (rx_enh_fifo_del         ),               //  output,    width = 4,         rx_enh_fifo_del.rx_enh_fifo_del
    .rx_enh_fifo_insert      (rx_enh_fifo_insert      ),               //  output,    width = 4,      rx_enh_fifo_insert.rx_enh_fifo_insert
    .rx_enh_highber          (rx_enh_highber          ),               //  output,    width = 4,          rx_enh_highber.rx_enh_highber
    .rx_enh_blk_lock         (rx_enh_blk_lock         )                //  output,    width = 4,         rx_enh_blk_lock.rx_enh_blk_lock
);
// =========================================================================
// ila and vio and error code to debug and monitor




endmodule
// ###################################################################################
// foot note of it
// please follow MIT when you want to ust it 